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Matx

Silicon Design-for-Test (DFT) Engineer

Who can apply: US-based role. The employer has not said which states are eligible — confirm before applying.
Location as listed by the employer: “Mountain View (HQ) or Remote”
Apply on Matx's site ↗

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About this role

Matx is hiring for a Silicon Design-for-Test (DFT) Engineer role (full-time). See the official posting for full details.

Requirements

  • Hands-on experience with DFT implementation — MBIST, at-speed scan and scan compression.
  • Strong knowledge of modern DFT standards and protocols: JTAG (IEEE 1149.1), IJTAG (IEEE 1687), and Streaming Scan Networks (SSN).
  • Experience or Working Knowledge of loading and validating PHY firmware via serial interfaces (SPI, I2C, or JTAG), including understanding of bootloader sequences and register map initialization.
  • Solid experience integrating PHY DFT interfaces (e.g., SERDES PHY test modes, analog test buses into the SoC DFT architecture.
  • Experience with system-level DFT access — hierarchical test access, test data compression, and multi-die/chiplet DFT — is a strong plus.
  • Familiarity with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, or equivalent.
  • Early Career - $160,000 - $275,000 + equity
  • Mid Career - $175,000 - $400,000 + equity

Summarized from the employer's posting — check the full posting for every requirement.